Exemplary embodiments of the present invention relate to a non-volatile memory device and a fabrication method thereof, and more particularly, to a non-volatile memory device having a three-dimensional (3D) structure where memory cells are formed along channels protruding perpendicular to a substrate, and a method for fabricating the same.
A non-volatile memory device retains data stored therein although a power source is cut off. At present, diverse non-volatile memory devices, such as flash memory, are widely used.
As the improvement in the integration degree of a two-dimensional memory device which is fabricated in a single layer over a silicon substrate reaches limitations, a three-dimensional non-volatile memory device which is fabricated by stacking a plurality of memory cells along channels protruding perpendicularly to a silicon substrate is introduced.
FIG. 1 is a cross-sectional view illustrating a three-dimensional non-volatile memory device.
Referring to FIG. 1, a first conductive layer 11 for forming a gate electrode of a pipe-channel transistor, a structure where a first inter-layer dielectric layer 12 and a second conductive layer 13 are alternately stacked to form a plurality of layers of memory cells, and a structure where a second inter-layer dielectric layer 16, a third conductive layer 17, and the second inter-layer dielectric layer 16 are sequentially stacked to form a selection transistor are disposed over a substrate 10.
A pair of cell channel holes is formed to penetrate the stacked structure of the first inter-layer dielectric layer 12 and the second conductive layer 13, and a pipe channel hole is disposed in the first conductive layer 11 to couple the lower portions of the pair of cell channel holes to each other. The pair of selection channel holes penetrates the stacked structure of the second inter-layer dielectric layer 16, the third conductive layer 17 and the second inter-layer dielectric layer 16.
A memory gate insulation layer 14 is disposed on the internal walls of the cell channel holes and the pipe-channel hole, and the cell channel holes and the pipe-channel hole where the memory gate insulation layer 14 is disposed are filled with a first channel layer 15. Also, a gate insulation layer 18 is disposed on the internal walls of the selection channel holes adjacent to the stacked structure of the second inter-layer dielectric layer 16, the third conductive layer 17 and the second inter-layer dielectric layer 16, and the portions of the selection channel holes where the gate insulation layer 18 is disposed are filled with a second channel layer 19.
As a result, a pipe channel transistor, multiple layers of memory cells, and a selection transistor are disposed over the substrate 10. The pipe channel transistor includes the first conductive layer 11, and the memory gate insulation layer 14 and the first channel layer 15 that are formed inside of the pipe channel holes. The multiple layers of memory cells include the memory gate insulation layer 14 and the first channel layer 15 that are formed inside of the pair of cell channel holes, and the second conductive layer 13 which is stacked vertically along the memory gate insulation layer 14 and the first channel layer 15. The multiple layers of memory cells along with one of the pair of cell channel holes and the multiple layers of memory cells along with the other of the pair of cell channel holes are separated from each other by a slit S. The selection transistor includes the gate insulation layer 18 and the second channel layer 19 that are formed inside of the pair of selection channel holes, and the third conductive layer 17. The selection transistor along with one of the pair of selection channel holes and the selection transistor along with the other of the pair of selection channel holes are separated from each other by the slit S.
In the structure of the three-dimensional non-volatile memory device described above, the channel layers are not directly coupled with the substrate. This means that the three-dimensional non-volatile memory device does not include a layer which functions as a substrate body where well pick-up regions are formed. Therefore, it is impossible to perform a data erase operation by applying an erase voltage to a substrate body in the known three-dimensional non-volatile memory device of FIG. 1, and instead, the known three-dimensional non-volatile memory device performs an erase operation by supplying holes based on a Gate-Induced Drain Leakage (GIDL) effect.
However, when an erase operation is performed based on the GIDL effect, the erase rate may decrease because holes are not sufficiently supplied. In particular, as the length of a channel layer disposed vertically increases, the erase rate further decreases.